4bit binary ripple counter with dflip flopside

As for when it should reset, if you want it to reset after it has been on for a whole tick if you do mean the clock tick not game tick , simply have the T flip flops reset on If your resetter lags like mine, you may want to reset on Where is the "reset of the memory " in the T flip-flop???

I am using design B on the wiki http: I am an EE, not a Minecraft expert. However, I can provide you some options, as redstone pretty much mirrors actual logic design. WrenAkula's suggestion is a very good one. However, to avoid insta-reset at , you have a couple of options. First, you could reset at instead.

Clock the D flip-flop, so that your reset only ever hits at the very beginning of the counter cycle you might even need to lead the counter clock a bit, depending on your timing. Another option would be to fully latch your ripple counter's output your design is called a ripple counter in EE terminology, btw.

For every output, add a D flip flop clocked out of phase of your main counter. They should only latch when your counter's outputs are all ready. This introduces a lag, but it's constant so it probably won't be a problem for your design. In addition, you don't need the extra redstone delays to compensate for the ripple with this design. You can also implement a fully synchronous counter. I'll leave it to you to search for this on the Internet.

Anything you find about digital and electronic logic design should apply to your redstone, as well. I was playing around with a similar design as Nocturnum's to count to 5, and I was struggling with timing the reset on due to the ripple it left me at A synchronous reset sounds like it might be easier to work with.

Thanks for the suggestions! Place a torch on the side of a block above your T flip flop. You want your torch to be above the reset of the memory cell in the T flip flop. As for when it should reset, if you want it to reset after it has been on for a whole tick if you do mean the clock tick not game tick , simply have the T flip flops reset on If your resetter lags like mine, you may want to reset on Where is the "reset of the memory " in the T flip-flop???

However, because the reset isn't instant, your output might be at for a little bit. You can avoid this problem by instead using a D flip-flop for a synchronous reset. Take your asynchronous reset output and feed it into the D input of a flip-flop. Clock the D flip-flop, so that your reset only ever hits at the very beginning of the counter cycle you might even need to lead the counter clock a bit, depending on your timing.

Another option would be to fully latch your ripple counter's output your design is called a ripple counter in EE terminology, btw. For every output, add a D flip flop clocked out of phase of your main counter. They should only latch when your counter's outputs are all ready. This introduces a lag, but it's constant so it probably won't be a problem for your design. In addition, you don't need the extra redstone delays to compensate for the ripple with this design.

You can also implement a fully synchronous counter. I'll leave it to you to search for this on the Internet. Anything you find about digital and electronic logic design should apply to your redstone, as well. I was playing around with a similar design as Nocturnum's to count to 5, and I was struggling with timing the reset on due to the ripple it left me at